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Circuit Note
Figure 2 shows the comparison of results between a typical CMOS
switch, with epitaxial layer, and the ADG5408 when subjected
to a latch-up test. During the test, a stress current is applied to
the pin for 1 ms, called the trigger, and the current at the pin is
measured after the trigger. This particular test is conducted with
the switch set to open, the drain (D) set to VDD, and the source
CN-0253
If computer control is desired, the EVAL-SDP-CS1Z is connected
to the EVAL-CN0253-SDPZ board using 120-pin mating
connectors.
Equipment Needed
? EVAL-CN0253-SDPZ board
(S) set to VSS, as depicted in Figure 3. The voltage of the source
is then driven beyond VSS until the required trigger current is
achieved. If latch-up has not occurred, then the current at the pin
returns to its pretrigger value. After latch-up has occurred, the
?
?
?
±18 V power supply
L-ion batteries
Digital voltmeter to measure output
pin continues to draw current without being driven by the trigger
voltage. This can only be stopped by powering down the part.
If controlling the EVAL-CN0253-SDPZ board using a PC is
required, additional requirements include the following:
From Figure 2, it can be seen that this typical CMOS switch reaches
a latch-up current at ?290 mA, while the ADG5408 did not latch
up until the test ended at ?510 mA.
10
?
?
?
PC with a USB port and Windows? XP or Windows
Vista? (32/64-bit) or Windows 7 (32/64-bit)
EVAL-SDP-CS1Z SDP
CN-0253 evaluation software
0
–10
–20
–30
Getting Started
In standalone usage only, the EVAL-CN0253-SDPZ , power
supplies, and test batteries are required.
To program the board with the PC, install the evaluation software.
To do this, load the evaluation software by placing the CN-0253
evaluation software CD in the CD drive of the PC. Using My
Computer , locate the drive that contains the evaluation software
–40
TYPICAL CMOS
ADG5408
CD and open the Readme file and follow the instructions for
installing and using the evaluation software.
–50
TRIGGER CURRENT (mA)
Figure 2. Post Latch-Up Trigger Current Comparison
V SS GND V DD
Functional Block Diagram of Test Setup
Figure 4 shows the test setup functional block diagram. The
EVAL-CN0253-SDPZ-SCH-Rev0.pdf file contains the complete
circuit schematics for the board. This file is contained in the
CN-0253 Design Support Package:
( http://www.analog.com/CN0253-DesignSupport ).
VSS
S
D
VDD
OPTIONAL
PC
Figure 3 . Latch-Up Test Configuration (Pretrigger) Common Variations
USB
DVM
COMMON VARIATIONS
For applications where four or less batteries are used in a stack,
the four differential channels of a single ADG5409 can be used.
The ADG5409 switches four differential inputs to a single
EVAL-SDP-CS1Z
A0 A1 A2 EN VOUT
120-PIN
J8
EVAL-CN0253-SDPZ
BAT 1
BAT 2
BATTERY
CELLS
differential output and has the same latch-up proof construction
as the ADG5408 .
5V POWER SUPPLY
J1-1
J1-2
J3-1
J3-2
J3-3
BAT 8
CIRCUIT EVALUATION AND TEST
+18V
COM
–18V
This circuit uses the EVAL-CN0253-SDPZ board and can be
used as a standalone board, or in conjunction with the EVAL-
SDP-CS1Z system demonstration platform (SDP) evaluation
board. In the standalone mode, the A0, A1, A2, and EN logic
levels can be controlled by links on the board or from external
sources connected to the board via SMB connectors.
Rev. A | Page 3 of 4
±18V POWER SUPPLY
Figure 4. Test Setup Functional Block Diagram
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